Just now, BIRENTECH rang the bell to go public! With GPUs in hand and orders exceeding 1.2 billion yuan, it has secured multiple domestic firsts.

Just now, Shanghai's leading GPU companyBIRENTECHListed on the Hong Kong Stock Exchangehit the market (of a new product)It has become the first domestic GPU company listed on the Hong Kong stock market and also the first new listing on the Hong Kong stock market in 2026.

The offering price was set at HK$19.60 per share (approximately RMB 17.60). The opening price surged by 82.141% to HK$35.70 per share (approximately RMB 32.05), with a market capitalization of HK$85.542 billion (approximately RMB 76.8 billion).

As of 9:35 a.m., BIRENTECH's stock price stood at HK$41.80 per share (approximately RMB 37.52), with a current market capitalization of HK$100.2 billion (approximately RMB 89.9 billion).

This leading domestic AI chip company, founded in 2019, reported revenue of ¥499,000 in 2022, which surged to ¥337 million by 2024, achieving a compound annual growth rate of 2500%. As of December 15, 2025, its backlog of sales orders stood at approximately ¥1.241 billion, which will translate into future revenue.

These figures reflect a Chinese AI chip company's sustained investment, consistent delivery, and continuous revenue growth.

Within China's AI chip sector, WallRidge Technology has achieved numerous technical milestones: it is the first company in China to package dual AI compute bare dies using 2.5D chiplet technology, pioneered support for advanced interconnect specifications within the industry, and its products support mainstream open-source large models such as DeepSeek, Qwen, and Llama. The company has demonstrated technological maturity in critical scenarios including training and inference for trillion-parameter large language models and multimodal models.

Its representative investors include state-owned platforms such as Shanghai State-owned Capital Investment Pioneer Fund, Shanghai Artificial Intelligence Industry Investment Fund, Guangzhou Industrial Investment, and Knowledge City Group; innovation technology and semiconductor investment funds like Qiming Venture Partners, Walden International, and Hillhouse Capital; as well as industrial investors including Ping An Group and Zhuhai Gree.

Based on its self-developed GPGPU architecture, Beren Technology has achieved a closed-loop system spanning chip design, software platforms, and system-level delivery, paving a sustainable path toward independent high-end computing power.

1. R&D expenditure accounts for 83.1% of total revenue, with patent applications ranking first among China's GPGPU companies.

In the GPU industry, a high proportion of R&D expenditure is not uncommon.

A standout feature in WallRise Technology's financial report is its “three highs”: the proportion of R&D personnel reaches 83.1%, R&D expenses account for over 70.1% of revenue, and the company ranks first among domestic GPGPU firms in the number of invention patent applications.

As of December 15, 2025, Bixin Technology has filed over 1,500 patent applications across multiple countries and regions worldwide, ranking first among Chinese GPGPU companies. The company has secured over 600 patent authorizations, placing it among the top Chinese GPGPU firms. Its invention patent authorization rate reached 100%, leading all domestic enterprises in this metric.

This has built a solid patent wall for its long-term development.

Compared to approaches like ASICs and FPGAs, GPGPU offers greater versatility and flexibility, dominating the mainstream AI chip market.

To enhance AI computing speed, GPGPU technology incorporates specialized hardware units and continuously upgrades memory capacity, bandwidth, interconnects, general-purpose flexibility, and energy efficiency.

BIRENTECH is among China's first GPGPU companies to incorporate PCIe 5.0, CXL, high-performance DRAM, and dual-die chiplet designs into commercial products. It also focuses on developing advanced technologies such as 3D stacking and CPO (co-packaged optics) to enhance AI computing system performance and scalability while reducing training and deployment costs for large models.

The company is the first and only Chinese GPGPU firm invited to present at Hot Chips, the world's premier chip design conference. It ranks among China's earliest GPGPU companies to achieve commercial deployment of a thousand-card cluster and pioneered the implementation of a point-to-point full mesh topology with eight GPU cards within a single server. Additionally, it has twice been honored with the SAIL Award (Outstanding AI Pioneer Award), the highest accolade at the World Artificial Intelligence Conference.

In the closed-group competition of MLPerf Inference 2.1, both the language processing model BERT and the image classification model ResNet50 achieved top rankings in the mass-produced chip category for both WallTech's GPGPU chip and the servers equipped with this chip.

Hong Zhou, CTO of BIRENTECH, oversees and sets the product's technical development direction and serves as the chief architect of Bixin Technology's GPGPU chips.

He possesses nearly 30 years of experience in GPGPU design and engineering solutions. He holds a Bachelor of Science degree from Peking University, a Master of Engineering degree from Tsinghua University, and a Master of Science degree from the State University of New York at Buffalo. He has served as Engineering Director at S3, Principal Architect at NVIDIA, Vice President of Hardware Architecture at S3 Graphics, and Chief Architect at Futurewei Technologies, Huawei's U.S. Research Center.

Zhang Linglan, COO of Bixin Technology, is responsible for project management, production, and quality control of Bixin Technology products.

He possesses over 23 years of experience in the semiconductor industry, holding a Bachelor of Electrical Engineering from Zhejiang University, a Master of Electrical Engineering from the University of Southern California, and a Master of Business Administration from the University of California, Berkeley. He has served as GPU SoC Architect at AMD, Senior R&D Manager at Samsung Electronics America R&D Center, and Vice President of Deep Computing at Higon Austin R&D Center Corporation.

Under their leadership, BIRENTECH continues to refine the five pillars of its comprehensive intelligent computing solution: proprietary GPGPU architecture, SoC design, hardware systems, software platforms, and cluster deployment optimization.

II. Our proprietary GPGPU architecture incorporates multiple innovations, with next-generation chips set to support FP8 and FP4 precision.

From architecture and encapsulation to system design, BIRENTECH's technical choices have always revolved around one fundamental premise:

Under established process conditions, how can computational power be further amplified?

Since initiating the development of its first-generation GPGPU architecture in 2019, BIRENTECH has launched multiple chips including the BR106, BR166, and BR110, covering cloud training, cloud inference, and edge inference scenarios.

Subsequently, the BR20X series is scheduled for commercial release in 2026, with enhanced support for data formats such as FP8 and FP4. The BR30X and BR31X series are planned for commercial release in 2028.

These are all based on the unified GPGPU architecture independently developed by Bixin Technology.

Constrained by manufacturing limitations, BIRENTECH opted for a “dual bare die + 2.5D packaging” approach to scale computing power, forging a viable path for continuous single-card performance enhancement.

For example, by co-packaging two BR106 die-sliced chips and four DRAMs, WallTech leverages die-slicing technology and die-to-die interconnect technology to launch the higher-performance BR166 chip product. Its performance reaches twice that of the BR106, with a die-to-die (D2D) bidirectional bandwidth of 896GB/s.

BIRENTECH has incorporated numerous innovations into the GPGPU architecture:

(1) Demonstrates outstanding general flexibility and AI acceleration capabilities: Utilizes a classic Single Instruction, Multiple Threads (SIMT) architecture to efficiently handle complex parallel computations.

(2) Advanced Tensor Core Architecture: The dedicated Tensor Core engine features a specialized design that significantly reduces the frequency of repeated data retrieval from DRAM during matrix operations. It supports data cycling, lowering bandwidth requirements for AI matrix computations, thereby substantially improving energy efficiency and computational performance.

(3) Asynchronous Data Transmission with Multicasting: Multicasting technology enables data to be read once from DRAM and simultaneously delivered to different computational cores, significantly accelerating large-matrix computations while reducing energy consumption.

(4) Near-Memory Computing: The chip integrates NUMA, UMA, L2 Reduction, and other storage technologies to automatically store data near computational cores. It performs reduction computations via L2, reducing the need to fetch data from remote DRAM and thereby improving data retrieval efficiency.

These designs enable the architecture to scale with expanding model sizes, parameter counts, and complexity, delivering high performance, universal flexibility, energy efficiency, and scalability—ultimately helping customers reduce total cost of ownership (TCO).

III. Not only competing on high performance, but also on stable and diverse delivery

To ensure successful chip operation, a comprehensive SoC design methodology is essential.

BIRENTECH possesses technical expertise in SoC architecture, memory systems, multi-GPU interconnects, SoC testing, SoC design flows, and chip packaging design. It is also an industry leader in supporting advanced interconnect specifications, with a focus on mass production stability and continuous delivery capabilities.

For example, the SoC architecture from BIRENTECH can flexibly configure varying numbers of SPC cores equipped with diverse heterogeneous computing modules based on the chip's AI application scenarios and target market segments. This configuration defines the memory system and interconnect structure accordingly. The memory system enhances effective bandwidth access for AI applications while reducing memory access latency. Multi-level partitioning technology and module reuse techniques simplify the physical design of complex modules in layout and routing, thereby improving the scalability of chip design.

In terms of interconnectivity, our proprietary BLink technology enables connections between GPU cards, achieving a maximum bidirectional data transfer rate of up to 64GB/s per channel across 4 to 8 channels. We pioneered the commercial deployment of GPU optical interconnect technology in China, driving advancements in all-optical networking and co-packaged optical technology.

Delivery-oriented, BIRENTECH offers a diverse product portfolio including PCIe (Peripheral Component Interconnect Express) boards, OAM (Open Accelerator Modules), and servers. It stands as one of China's first GPGPU companies to successfully develop, prototype, and mass-produce high-performance OAMs and universal backplanes.

PCIe is suitable for customers requiring a balance between performance and cost, while OAM caters to those demanding the highest performance. Servers provide ready-to-use computing power. Servers can be interconnected into supernodes and further scaled into server clusters.

The next-generation product will upgrade to 700W air cooling and 1000W liquid cooling. The UBB can connect up to eight OAM cards with various topologies via its internal P2P interface. It will also feature more flexible and powerful SerDes connections to enable vertical scaling of the system.

The ultimate success of data center GPUs hinges not on single-card performance, but on their scalability for cluster deployment. This is also the key factor determining whether chip companies can cross the commercialization tipping point.

BIRENTECH has developed comprehensive solutions for large-scale intelligent computing clusters by integrating its proprietary hardware systems and software platforms with other hardware infrastructure provided by partners, including servers, storage, and network equipment.

IV. For developers, software and clusters are the true barriers to entry.

The stability of computing power systems is amplified in real-world implementation. For a GPU company, an in-house software platform is both the key to fully leveraging computing and communication capabilities and the foundation for expanding its ecosystem.

BIRENTECH's chosen software path balances reducing migration costs with preserving autonomy for future evolution.

Its self-developed computing software platform BIRENSUPA provides programming interfaces, algorithm libraries, training and inference frameworks, and a complete toolchain. It is also compatible with third-party GPGPU computing software platforms, significantly reducing the cost of migration to BIREN Technology's GPGPU products.

The BIRENSUPA programming model is compatible with mainstream GPGPU programming models in the industry. Its proprietary GPGPU compiler optimizes resource utilization and enhances efficiency by converting high-level code into BIRENSUPA's exclusive instruction set. Additionally, a suite of proprietary libraries accelerates various application domains.

At the model level, BIRENSUPA natively optimizes mainstream open-source models such as DeepSeek, Qwen, and Llama, simplifying the development and deployment of AI solutions. Its Model Zoo hosts AI models natively optimized for BIRENSUPA, enabling customers to deploy pre-trained models or develop their own models based on reference implementations.

Meanwhile, Bixin Technology has launched over 30 joint projects with prestigious universities including Tsinghua University, Fudan University, Shanghai Jiao Tong University, and Zhejiang University, continuously nurturing a local GPU developer ecosystem.

At the cluster level, BIRENCUBE Cluster Management Platform by BIRENCUBE Technology is designed to manage extensive AI hardware infrastructure. It integrates proprietary hardware and software with servers, storage, and networking equipment to form an end-to-end solution, enabling customers to build GPU cluster systems comprising tens of thousands of GPGPU chips.

Its intelligent computing cluster solutions lead the industry in reliability and performance, as well as universal flexibility and compatibility:

• Qianka cluster training has operated continuously for over 30 days without interruption and fault-free for over 5 days.
• Industry-first three-level asynchronous checkpointing enhances reliability and reduces access overhead;
• Qianka Cluster restores trillion-parameter models to the last checkpoint within 5 minutes, delivering industry-leading speed.
• The loss function achieved zero error after multiple consecutive training sessions and continued to decrease after a one-month training cycle.
• Supports mainstream large models, delivers industry-leading performance, and achieves a linear acceleration ratio of 951 TP4T per thousand-card cluster.
• Automated parallel optimization for large models, featuring industry-first asynchronous offloading to overcome memory bottlenecks;
• Comprehensive model support, collaborating with upstream and downstream partners to build an ecosystem supporting over 50 large models;
• Open ecosystem, compatible with three types of heterogeneous software acceleration platforms;
• Through direct optical interconnects, optical circuit switching, and other interconnection methods, it supports hyperscale nodes with high scalability and flexible topologies, enabling more efficient operation of large-scale models.

In 2024, BIRENTECH deepened collaborations with strategic clients, securing landmark projects such as commercial AIDC Qianka GPU clusters. The company deployed its GPGPU clusters in 5G new call and other application scenarios, establishing partnerships with all three major Chinese telecom operators. It continues to validate the reliability and competitiveness of its solutions in large-scale deployment environments.

As of June 22, 2025, BIRENTECH has served 9 Fortune China 500 companies, including 5 listed on the Fortune Global 500. The company has strategically expanded into key industries such as AI data centers, telecommunications, AI solutions, energy and utilities, fintech, and internet.

Conclusion: Domestic GPUs Move Toward Large-Scale Deployment

Compared to international giants, domestic GPUs objectively lag in ecosystem maturity, developer scale, and software toolchain sophistication. However, as overseas GPU supply becomes increasingly unstable, downstream industries are embracing alternatives to CUDA, enabling domestic GPUs to transition from merely viable to scalable solutions.

In the capital market, few companies truly possess both GPGPU architecture and proprietary software platforms alongside system-level delivery capabilities. BIRENTECH advanced architecture, packaging, software, and systems in parallel at an early stage, laying the foundation for its large-scale clusters and long-term evolution.

Compared to global competitors, this technological expertise combined with localized knowledge in China and on-site customer support capabilities enables Biring Technology to establish strategic partnerships with major clients in key industries, deeply understanding and meeting their unique requirements.

After going public, the market will observe how these projects perform over a longer time horizon.

Source: Smart Stuff